1. Field of the Invention
The present invention relates to a power supply circuit and more particularly, to a power supply circuit converting an external power supply potential into an internal power supply potential to supply the internal power supply potential to a load and a configuration of a semiconductor memory device with the same.
2. Description of the Background Art
A withstand voltage of an internal circuit of a semiconductor device has been reduced through progress in microfabrication according to increased requirement for a larger capacity of a semiconductor memory device. In order to cope with such a situation, in a semiconductor memory device, an external power supply potential, for example, of 5V or 3.3V is stepped down to a proper internal power supply potential (for example, 2.5 V, 2.0V or the like) by a power supply circuit provided internally (hereinafter also referred to as an internal power supply circuit). Such an internal power supply circuit is referred to as a voltage down converter (VDC) as well.
When an internal power supply potential generated by a power supply circuit is reduced to a value lower than a prescribed level, a group of internal circuits of a semiconductor memory device has a risk that neither of the internal circuits can perform a prescribed operation at a prescribed speed since the internal power supply potential is used by each of the internal circuits in the semiconductor memory device. On the other hand, when the internal power supply potential rises and exceeds a prescribed level, there arises a risk that not only does power consumption increase, but transistors miniaturized due to progress to higher integration are also electrically broken. Hence, the power supply circuit has to control a level of the internal power supply potential in a stable manner such that fluctuations in the internal power, supply potential are confined within a prescribed range determined by specifications of the semiconductor memory device.
FIG. 31 is a circuit diagram representing a configuration of a prior art internal power supply circuit 500 having a typical configuration of VDC.
The internal power supply circuit 500 is a circuit for receiving an external power supply potential ext.Vdd from an external power supply line 510 to hold an internal power supply potential int.Vdd supplied to a load 550 at a reference voltage Vref.
Referring to FIG. 31, the internal power supply circuit 500 includes: an external power supply line 510 supplying an external power supply potential ext.Vdd; an internal power supply line 520 supplying an internal power supply potential int.Vdd; a potential difference amplifying circuit 530 amplifying and outputting a potential difference between the internal power supply potential int.Vdd and a reference potential Vref; a current supply transistor QD1 supplying a current Isup to the internal power supply line 520 from the external power supply line 510 according to an output of the potential difference amplifying circuit 530; and an stabilization capacitance 545 for suppressing fluctuations in potential level of the internal power supply line 520. The load 550 receives supply of the internal power supply potential int.Vdd from the internal power supply line 520 and consumes a load current Iload.
The potential difference amplifying circuit 530 includes P type MOS transistors QP1 and QP2, and N type MOS transistors QN1, QN2 and QN3 constituting a current mirror amplifier coupled between the external power supply line 510 and a ground line 540. The reference voltage Vref and the internal power supply potential int.Vdd are inputted to the respective gates of the transistors QN1 and QN2. The gates of the transistors QP1 and QP2 are coupled to a node Np. The transistor QN3 supplies an operating current of the current mirror amplifier in response to activation of a control signal ACT.
The transistors QP1, QP2, QN1, QN2 and QN3 are designed in such a manner to operate in respective saturation regions and thereby, the potential difference amplifying circuit 530 amplifies differentially a gate potential difference of the transistors QN1 and QN2 such that the gate potential difference is reflected on a potential level of a node Nd.
When an internal power supply potential int.Vdd is lower than the reference potential Vref, a potential level of the node Nd is shifted to the ground potential Vss side and in response to the shift, the current supply transistor QD1 supplies a current to the internal power supply line 520 from the external power supply line 510. On the other hand, when an internal power supply potential int.Vdd rises beyond the reference potential Vref, a potential level of the node Nd is shifted to the external power supply potential ext.Vdd side; therefore, the current supply transistor QD1 is turned off to stop current supply to the internal power supply line 520. With such operations, the internal power supply circuit 500 compensates for fluctuations in the internal power supply potential int.Vdd to hold the internal power supply potential int.Vdd at a level of the reference potential Vref.
However, various patterns exist in current consumed by the load 550 receiving supply of an internal power supply potential int.Vdd from the internal power supply line 520.
FIG. 32 is a timing chart representing operation of the internal power supply circuit corresponding to an example pattern of current consumption of the load 550. In FIG. 32, shown is a current waveform of a load consuming a small amount of current continuously. As a typical example load having such as current consumption pattern, there can be named a peripheral circuit such as a signal buffer used in a DRAM (Dynamic Random Access Memory).
Referring to FIG. 32, the internal power supply circuit is active during a period when a control signal ACT is active. Since a load current Iload of the load 550 is continuously consumed, no much difference occurs between an instant value I1 and an average value of the load current. Hence, a drop xcex94V1 in level of an internal power supply potential int.Vdd can be suppressed to a comparatively low level by the action of the stabilization capacitance 545.
Therefore, the current supply transistor QD1 can follow gradual reduction in potential level occurring on the internal power supply line 520 by the action of the current Isup controlled by the potential difference amplifying circuit 530 and supplied to the internal power supply line 520. As a result, the internal power supply potential int.Vdd never decreases lower than the reference potential by a great difference. Consequently, there is a low possibility to produce a problem such as malfunction in the internal circuitry, which is a load receiving supply of the internal power supply potential.
FIG. 33 is a timing chart representing operation of an internal power supply circuit corresponding to another example pattern of load current consumption. In FIG. 33, shown is a current waveform of a load consuming a load current Iload with a large amplitude, supplied intermittently. As a typical example of a load with such a current consumption pattern, there can be named a sense amplifier used in a DRAM.
In a case of FIG. 33 as well, the internal power supply circuit is active during a period when a control signal ACT is active. However, in a case of a load current with a large amount, supplied intermittently, a large difference occurs between an instant value I2 and an average value of a load current; therefore, an internal power supply potential int.Vdd cannot be sufficiently held by the action of a supply current Isup of the current supply transistor QD1 controlled by the potential difference amplifying circuit 530. As a result, a drop xcex94V2 of the internal power supply potential is rendered larger. With a large value in the drop xcex94V2, there arises a possibility to deteriorate operation of an internal circuit, which is a load receiving supply of an internal power supply potential.
When suppression of a drop in level of an internal power supply potential int.Vdd is intended by use of the stabilization capacitance 545 in the presence of such a rapidly changing load current with a large amplitude, the capacitance 545 has to be of a large value, thereby causing a new problem of increase in chip area.
A technique is disclosed, for example, in Japanese Patent Laying-Open No. 6-266452 for maintaining an internal power supply potential in a stable manner without largely depending on a stabilization capacitance while coping with such a rapidly changing current consumption, which technique specifies an internal power supply circuit forcibly supplying a current onto an internal power supply line in a timing matching with current consumption.
In an internal power supply circuit applied with such a technique, it is important that timing at which to perform forced current supply is properly adjusted according to current consumption timing in a load. When timing at which to start forced current supply is later than timing at which to start of current consumption by a load, a large drop in internal power supply potential takes place, while on the other hand, when timing at which to stop forced current supply is too late, the internal power supply line 520 is overcharged to raise the internal power supply potential in excess, which leads even to a risk to cause inconvenience to the contrary.
It is an object of the present invention to provide a power supply circuit capable of stably maintaining an internal power supply potential even to a load consuming a rapidly changing current and a configuration of a semiconductor memory device with the same circuit.
The present invention will be summarized as follows:
An aspect of the present invention is directed to a power supply circuit converting an external power supply potential into an internal power supply potential to supply the internal power supply potential to a load circuit performing a prescribed operation in response to activation of a control signal, and including: an external power supply line; an internal power supply line; a potential difference amplifying circuit; a current supply circuit; and a forced current supply control circuit. The external power supply line supplies an external power supply potential. The internal power supply line, coupled to the load circuit, supplies an internal power supply potential. The potential difference amplifying circuit amplifies a potential level difference between the internal power supply potential and a reference potential to output the amplified potential level difference to a control node. The current supply circuit supplies a supply current amount according to a potential level of the control node to the internal power supply line from the external power supply line. The forced current supply control circuit forcibly performs current supply to the internal power supply line from the external power supply line, regardless of the potential level difference, according to an auxiliary control signal activated for performing a preliminary operation performed in advance of said prescribed operation and said control signal. The forced current supply control circuit forcibly performs current supply during a prescribed period from a first time point determined in response to activation of the auxiliary control signal till a second time point determined in response to activation of the control signal.
A main advantage of the present invention is, accordingly, that a current can be forcibly supplied to the internal power supply line, before a prescribed operation gets started in a load circuit to consume a current, according to a control signal corresponding to a preliminary operation performed in advance of the prescribed operation. As a result, even when a consumed current by the load circuit rapidly increases to a large amount, a drop in internal power supply potential is suppressed and the prescribed operation of the load circuit can be performed with no trouble, in a situation where a large stabilization capacitance is not provided on the internal power supply line.
Another aspect of the present invention is directed to a semiconductor memory device including: a memory cell array; a plurality of word lines; a plurality of bit line pairs; a plurality of sense amplifier circuits; and a power supply circuit. The memory cell array includes a plurality of memory cells arranged in a matrix pattern. The plurality of word lines are provided corresponding to respective rows of the memory cells and at least one of the plurality of word lines is selectively activated in response to activation of a first control signal. The plurality of bit line pairs are provided corresponding to respective columns of the memory cells and each bit line pair transmits data held in a memory cell corresponding to an activated word line. The plurality of sense amplifier circuits are provided corresponding to the respective plurality of bit line pairs and each sense amplifier circuit amplifies a potential level difference occurring between bit lines constituting a corresponding one of the plurality of bit line pairs in response to a second control signal. The power supply circuit converts an external power supply potential into an internal power supply potential. The power supply circuit includes: an external power supply line supplying an external power supply potential; an internal power supply line coupled, at least, to a sense amplifier to supply an internal power supply potential to the sense amplifier; a potential difference amplifying circuit amplifying a potential level difference between the internal power supply potential and a reference potential to supply the amplified potential level difference to a control node; a current supply circuit for supplying a supply current amount according to a potential level of the control node to the internal power supply line from the external power supply line; and a forced current supply control circuit for forcibly performing current supply to the internal power supply line from the external power supply line, regardless of the potential level difference, according to the first and second control signals. The forced current supply control circuit forcibly performs current supply during a prescribed period from a first time point determined in response to activation of the first control signal till a second time point determined in response to activation of the second control signal.
Hence, a current can be forcibly supplied to an internal power supply line before a sense amplifier is activated and a current is consumed. As a result, a drop in internal power supply potential is suppressed and a data read operation by a sense amplifier circuit can be performed at high speed without providing a large stabilization capacitance onto the internal power supply line while coping with consumption of a rapidly changing, large amount of current by a sense amplifier circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.